1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of highly conformal spacer elements, also referred to as L-shaped spacers, during the manufacturing of conductive lines, such as a gate electrode of a field effect transistor.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. Typically, the gate electrode of a field effect transistor may be considered as a conductive line, which is comprised in standard CMOS technology of highly doped polysilicon including a metal silicide region, wherein the lateral extension of the conductive line substantially determines the length of a conductive channel being formed in a silicon region under a gate insulation layer that separates the gate electrode and the silicon region. This channel region connects highly doped drain and source regions, the dopant profile of which is typically generated by complex ion implantation sequences in which the gate electrode acts as an implantation mask. As the dimensions of a field effect transistor decrease, typically the channel length, i.e., the lateral extension of the gate electrode, has to be decreased in combination with a thickness of the gate insulation layer so as to maintain a required degree of controllability of the conductive channel forming in the channel region upon application of an appropriate control voltage to the gate electrode. In addition, precisely controlled dopant profiles in the lateral and the vertical direction are required so as to reduce adverse effects, such as hot carrier effects and short channel effects, that may increasingly occur when the dopant profile is not adequately adapted to the overall transistor dimensions.
Commonly, the lateral dopant profile is adjusted by providing an implantation mask, wherein the material composition and layer thickness in combination with the lateral dimensions of the mask enable the creation of a specified lateral dopant profile during a specifically designed implantation process. That is, process parameters of the implantation process, i.e., the type of dopants used, the particle energy, tilt angle, and the like, are selected on the basis of the characteristics of the implantation mask so as to achieve the required dopant profile. Therefore, it has become standard practice in conventional CMOS technologies to provide sidewall spacers adjacent to the gate electrode, wherein a lateral width of the sidewall spacers allows a precise control of the lateral blocking effect during an implantation sequence. Although a plurality of materials are typically used for the sidewall spacers, it turns out that, for extremely scaled transistor devices, silicon nitride is a preferred candidate since it may be deposited by well-established plasma enhanced chemical vapor deposition (PECVD) techniques in a highly conformal manner, wherein a thickness of the silicon nitride layer of this order of magnitude may suppress boron diffusion more efficiently compared to a oxide layer. The sidewall spacer formation process is a self-aligned technique in which the silicon nitride layer is conformally deposited over the substrate including the gate electrode structure and is subsequently anisotropically etched back to leave behind the spacer elements on the sidewalls of the gate electrode, whereas other substrate regions are substantially cleared of silicon nitride. Since an etch chemistry for anisotropically etching silicon nitride is typically based on hydrogenated carbon fluorides, exposure of non-protected silicon surfaces, such as a top surface of the polysilicon gate electrode and the crystalline silicon of the substrate, would lead to a significant etching of these exposed silicon areas. Consequently, a thin liner oxide is typically formed, for instance, by oxidation or deposition, prior to the formation of the silicon nitride layer, wherein the anisotropic etch chemistry used for removing the silicon nitride layer exhibits an excellent selectivity to silicon dioxide, thereby substantially avoiding undue material removal of the underlying silicon areas. The silicon dioxide may also be used during subsequent implantation processes to reduce channeling effects. In other process flows, the thin silicon dioxide layer may be removed by a so-called “breakthrough” step using, for instance, a hydrogenated fluorine (HF) wet etch. Since the formation of silicon nitride sidewall spacers has become a standard technique in the manufacturing of advanced CMOS devices, highly efficient anisotropic etch recipes have been developed that provide a high silicon nitride etch rate. Moreover, the process recipes may be optimized in terms of required process gases and tool utilization so that a minimum number of different reactive gases are required in a single etch tool for performing the silicon nitride etch.
Although the above-described sidewall spacer technique is very efficient in the fabrication of CMOS devices having a gate length well beyond 0.2 μm, it turns out that for smaller feature sizes the formation of relatively bulky sidewall spacers may be disadvantageous in view of thermal stress exerted to the gate electrode and caused by the formation of the sidewall spacers. Additionally, bulky sidewall spacers may not provide the required flexibility in designing the lateral dopant profile of the drain and source regions and the corresponding extension regions connecting to the channel region. For this reason, highly conformal spacer elements, so-called L-shaped spacers, have been proposed to at least partially reduce stress effects in the gate electrode while providing an increased variability of subsequent implantation processes. In other process schemes, bulky spacers are still used for the implantation, while L-shaped spacers are then formed after removal of the bulky spacers to avoid undesired implantation through the foot of the L-shaped spacer, so as to enable more efficient exposure of the upper portion of the gate electrode prior to the silicidation.
With reference to FIGS. 1a–1d, a typical conventional process flow for forming L-shaped sidewall spacers will now be described in more detail. In FIG. 1a, a field effect transistor 100, shown in an early manufacturing stage, comprises a substrate 101 including a silicon region in which drain and source regions are to be formed adjacent to a channel region 104. A gate electrode 102, typically comprised of polysilicon, is formed above the channel region 104 and is separated therefrom by a gate insulation layer 103, which may be comprised, for instance, of silicon dioxide. Moreover, a liner oxide 105 is formed on the substrate 101 and on the gate electrode 102. It should be noted that, for convenience, isolation structures in the form of trench isolations or localized oxidized substrate portions as well as any offset spacers are not shown.
A typical process flow for forming the transistor 100 as shown in FIG. 1a may comprise the following processes. After formation of isolation structures (not shown), a vertical dopant profile may be formed within the substrate 101 and especially within the channel region 104 by well-established implantation sequences. Thereafter, a gate electrode layer stack is formed on the substrate 101, wherein the gate electrode layer stack comprises a gate dielectric and formed thereon a polysilicon layer of appropriate thickness. The gate dielectric may be comprised of any appropriate material with a required thickness and may, for instance, be comprised of silicon dioxide with a thickness of approximately 2–3 nm or less for advanced transistor devices. The gate dielectric may be formed, when comprised of silicon dioxide, by advanced oxidation and/or growth techniques. Subsequently the polysilicon layer may be deposited by well-established low pressure CVD methods. Then, a resist mask (not shown), possibly including a bottom anti-reflective coating, is formed on the polysilicon layer by means of advanced photolithography, wherein an anisotropic etch process is then performed so as to pattern the gate electrode 102. The gate dielectric, acting as an etch stop layer during the patterning of the gate electrode 102, may be patterned by a corresponding HF-based clean process, in which etch passivant layers are removed, thereby removing exposed portions of the gate dielectric so as to form the gate insulation layer 103. The liner oxide 105 may be formed by oxidation and/or deposition techniques such as plasma enhanced CVD. Typically, a thickness of the liner oxide 105 may be in the range of approximately 3–15 nm.
FIG. 1b schematically shows the transistor 100 in an advanced manufacturing stage. The transistor 100 comprises a conformal silicon nitride layer 106 having a thickness indicated by 106a. As will be shown later, the thickness 106a of the silicon nitride layer substantially defines a thickness of the conformal, i.e., L-shaped, spacers to be formed. A second spacer layer 107 is conformally formed on the silicon nitride layer 106 and has a thickness 107a that substantially determines a length of the conformal spacers, as will be explained later on.
The silicon nitride layer 106 may be formed by a low temperature plasma enhanced CVD process, wherein the physical characteristics of the layer 106 may be adjusted by correspondingly selecting the deposition process parameters. As previously noted, silicon nitride and any processes for depositing the same are highly approved in the formation of conventional bulky sidewall spacers so that conformity and layer thickness of the layer 106, as well as the characteristics of the material composition, may be well controlled so as to provide the required spacer characteristics. Thereafter, the spacer layer 107 is deposited, wherein frequently organic materials, amorphous silicon, or silicon dioxide are used as preferred materials. Depending on the type of material used, an appropriate deposition technique is selected so as to form the layer 107 having the required thickness 107a. Although the spacer layer 107 is shown in the form of a relatively conformal layer which may be appropriate for silicon or silicon dioxide, in other examples the layer 107 may be provided as an organic material that is applied by spin-on techniques, wherein, depending on the degree of viscosity of the organic material, a thickness of the layer 107 on top of the gate electrode 102 may significantly differ from the thickness 107a. 
FIG. 1c schematically shows the transistor 100 with substantial portions of the spacer layer 107 being removed, thereby forming sacrificial sidewall spacers 107b. If the spacer layer 107 is comprised of, for instance, silicon dioxide, a correspondingly designed anisotropic etch process may be performed so as to substantially completely remove horizontal layer portions of the layer 107 while only slightly attacking the silicon nitride layer 106. To this end, an anisotropic etch process on the basis of carbon and fluoride may be performed, wherein the achieved etch selectivity to the underlying silicon nitride layer 106 and/or the available thickness 106a thereof substantially determine an allowable over-etch time for exposing upper sidewall portions 108 of the silicon nitride layer 106. As previously explained, the initial thickness 107a substantially determines the lateral extension of the sidewall spacer 107b when the spacer layer 107 has been deposited in a substantially conformal manner. If the sacrificial sidewall spacer 107b is formed on the basis of the spacer layer 107 being deposited in a non-conformal manner, for instance by spin-on techniques, the resulting width of the spacer 107b may be adjusted by the specifics of the etch process for removing the excess material of the spacer layer 107. The corresponding behavior of the etch process may be determined in advance so that the resulting width of the sacrificial spacer 107b may be achieved with a required precision irrespective of the degree of conformity of the initial spacer layer 107.
At any rate, a specific etch process has to be performed so as to obtain the sacrificial spacer 107b having the desired width. Consequently, additional reactive gases or other precursors required for the appropriate etch chemistry have to be provided in combination with a suitable etch tool, thereby contributing to process complexity. Thereafter, exposed portions of the silicon nitride layer 106 may be removed by a well-established anisotropic etch step using an etch chemistry similar to that used in conventional processes for manufacturing bulky silicon nitride sidewall spacers, wherein the etch process is reliably stopped within the liner oxide 105. Next, the sacrificial spacers 107b may be removed by a correspondingly designed etch process wherein, depending on the material composition of the sacrificial spacer 107b, exposed portions of the silicon oxide liner 105 may be removed prior to, during, or after the removal of the sacrificial spacers 107b. For instance, if the sacrificial spacers 107b are comprised of silicon dioxide, the liner oxide 105 may be removed along with the sacrificial spacers 107b in a common etch process. For instance, a substantially isotropic etch process, such as an HF wet etch process, may be performed that typically exhibits a superior etch selectivity to silicon, compared to an anisotropic etch process, at a reduced degree of damage caused to the underlying silicon areas owing to the substantial absence of high energetic ionized particles directed to the substrate surface.
FIG. 1d schematically shows the transistor 100 after removal of the sacrificial spacers 107b and exposed portions of the oxide liner 105, wherein, for convenience, any undercut regions at the upper sidewall portions 108 and at the foot of the resulting L-shaped spacers, indicated as 106b, are not shown. As is evident from FIG. 1d, the conformal spacer or L-shaped spacer 106b exhibits a spacer length, denoted as 106l , which is substantially determined by the width of the sacrificial spacer 107b (see FIG. 1c) and by the initial layer thickness of the silicon nitride layer 106. Moreover, a thickness of the L-shaped spacer 106b, denoted as 106t, is substantially determined by the initial layer thickness 106a of the silicon nitride layer 106. Moreover, as may be seen from the drawing, the initial thickness of the liner oxide 105 may contribute to the spacer length 106l as well as to the spacer thickness 106t. 
In a subsequent implantation sequence, an efficient lateral dopant profiling may occur, wherein the resulting dopant profile may be controlled, in addition to appropriately selecting the implantation parameters, by the spacer length 106l and the spacer thickness 106t, wherein, additionally, the reduced material amount of the L-shaped spacer 106b may provide superior stress-induced effects on the gate electrode 102.
Although the L-shaped spacer 106b may provide an improved lateral dopant profiling in combination with reduced stress-induced effects, a complex etch sequence is required for forming and removing the sacrificial spacers 107b, thereby resulting in the introduction of additional reactive gases and/or the establishment of new etch recipes and/or the requirement for additional etch tools. For instance, the sacrificial spacers 107b require an oxide etch process that stops on nitride, while a subsequent nitride spacer etch relies on the etching of nitride with oxide as etch stop layer. Due to etch gas residues from the previous step or different tool hardware requirements for the different etch processes, typically two different etch chambers may be needed. In view of these drawbacks, a need exists for a manufacturing technique that enables the formation of L-shaped spacers without unduly contributing to process complexity.